Apparatus And Method For Serial To Parallel In An I/O Circuit

ABSTRACT

A serial to parallel I/O circuit apparatus includes M sequential logic circuits and each of them includes a first D-type flip-flop for receiving one bit of input data, and the output of each the first D-type flip-flop connects to the input of a first D-type flip-flop of a next stage. A second D-type flip-flop receives one bit of enable control signal, and the output of each of the second D-type flip-flops connects to the input of a second D-type flip-flop of a next stage. A multiplexer contains two input terminals and an enable control signal receiving terminal, wherein one input terminal is used to receive the input data received by the first D-type flip-flop, and the enable control signal receiving terminal receives the enable control signal received by the second D-type flip-flop. A D-type latch outputs the data, and the output data is fed back to another input terminal of the multiplexer so as to be selected as a data output when a next set of data are input.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to an apparatus and method for an I/Ocircuit, in particular to an apparatus and method for serial to parallelin an I/O circuit.

2. Description of the Prior Art

In general, the number of pins of an IC is fixed after beingmanufactured. In the meantime, because of the trend of an SOC (system ona chip), a part of the pins must be shared so as to achieve an object ofreducing IC size. Therefore, under the limitation of pin counts and thetrend of SOC, it is an inevitable result that a single pin hasmulti-functions.

As shown in FIG. 1, a pin of an IC designed by using the concept of asingle pin with a multifunction can possess many functionssimultaneously, but at one time only a function can enable (i.e., thepin can be used by selecting only one of those functions each time).Thus a next function will not be shifted to until the present functionis completed. Its speed is slower than that of an IC without anymultifunction pin, and therefore is only suitable for use in arelatively slow bus. In addition, an additional pin as a chip selectshould be provided for function switching in the above architecture.

Generally, in order to overcome the advantage of insufficient outputpins, such a way of a sequential logic circuit (as shown in FIG. 2A) maybe used to extend pins. An I/O circuit can be formed by combining aplurality of sequential logic circuits, and each of which can processone bit of data. If there is a need to increase the number of outputs,it only needs to increase the number of the sequential logic circuits(as shown in FIG. 2B). Each sequential logic circuit comprises a D-typeflip-flop and a D-type latch. For an M-bit input data stream I (I₀ . . .I_(M−3)I_(M−2)I_(M−1)), one bit of the input data is input into theD-type flip-flop of the first sequential logic circuit each time inaccordance with the bit sequence thereof. After the D-type flip-flopreceives a set of input data, it will transfer the previously receivedinput data to a next stage D-type flip-flop. When the input of datastream I (I₀ . . . I_(M−3)I_(M−2)I_(M−1)) is completed, triggered by aclock signal CLK, the written input data stream I (I₀ . . .I_(M−3)I_(M−2)I_(M−1)) is output to a corresponding D-type Latch forlatching. Finally, triggered by another clock signal Load, the datastream I (I₀ . . . I_(M−3)I_(M−2)I_(M−1)) is outputted, where M isgreater than or equal to the number of the sequential logic circuits.

For example, FIG. 2C shows an 8-bit I/O circuit 200, which includes 8sequential logic circuits. Firstly, the D-type flip-flop D₀ of a firstsequential logic circuit 210 receives a first set of input data 10 of aM-bit input data stream I (I₀ . . . I_(M−3)I_(M−2)I_(M−1)) (M>=8) as itsinput data. Thereafter, when a second set of input data I₁ is input intothe first D-type flip-flop D₀, I₀ is sent to the D-type flip-flop D₂ ofthe second sequential logic circuit 220 as its input data. Then, after athird set of input data I₂ is input into the first D-type flip-flop D₀,I₁ is sent to a second D-type flip-flop D₁ while I₀ is transmitted to athird D-type flip-flop D₂, . . . etc. After the input of all the datastream I (I₀ . . . I_(M−3)I_(M−2)I_(M−1)) (M>=8) is completed, beingtriggered by the clock signal CLK, the input data are outputted tocorresponding D-type latches (for example, the first D-type flip-flop D₀corresponds to a first gating latch D_(G0)), respectively, and thecorresponding gating latches latch their input data, respectively.Finally, being triggered by a clock signal Load, all the input datastream I (I₀ . . . I_(M−3)I_(M−2)I_(M−1)) (M>=8) are outputtedsimultaneously. Before the input data stream I (I₀ . . .I_(M−3)I_(M−2)I_(M−1)) (M>=8) is written in, a clear signal CLR may beused to clear out the input data written previously in the D-typeflip-flops. As can be seen from the input and output statuses in Table1, the system will not output data until it is written in at least 8bits.

FIG. 3 shows an operational flowchart of an existing I/O circuit, andthe steps of which are described as follows:

Step 310: a clear signal CLR is inputted to clear out the input datawritten previously;

Step 320: the input data stream I (I₀ . . . I_(M−3)I_(M−2)I_(M−1))(M>=8) is input into the first D-type flip-flop one bit each time inorder of bit, and when a next set of input data are inputted, theprevious set of input data will be pushed to a next stage D-typeflip-flop;

Step 330: after the input of the data stream I (I₀ . . .I_(M−3)I_(M−2)I_(M−1)) (M>=8) is completed, triggered by the clocksignal CLK, the input data are outputted to corresponding D-type latchesfor latching, respectively; and

Step 340: triggered by the clock signal Load, the input data stream Ilatched by the D-type latch is output.

As can be seen from the above descriptions, the sequential logiccircuits are designed with additional output pins in a series connectionmanner so as to overcome the problem of insufficient output pins in anIC. However, the output will not be performed until all the sequentiallogic circuits are fully written in each time, which might affect thewhole system performance because of slow data transmission rate.

SUMMARY OF THE INVENTION

The present invention provides an apparatus and method for serial toparallel of an I/O circuit that enables an IC circuit to deliver inputdata quickly and efficiently, in addition to extending the output pins.

An I/O circuit for serial to parallel according to an embodiment of thepresent invention comprises M sequential logic circuits in seriesconnection, each of which processes one bit of data, and the number ofthe sequential logic circuits may be increased as needed so as to extendthe number of I/Os. Each sequential logic circuit includes two D-typeflip-flops, a multiplexer, and a D-type latch. These two D-typeflip-flops receive an input data and an enable control signal,respectively, while the multiplexer selects the type of output data. TheD-type latch latches and outputs the data from the multiplexer.

A method for serial to parallel of an I/O circuit according to anembodiment of the present invention is as follows. Firstly, an N-bitinput data stream is input one bit each time according to bit sequence.Secondly, the system determines, according to the status (high level orlow level) of an enable control signal input synchronously, whether tooutput the input data or output a feedback data, which was outputpreviously (remain unchanged).

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a schematic diagram showing the output of an IC with the pinmultifunction concept.

FIG. 2A is a schematic diagram of a sequential logic circuit.

FIG. 2B is a schematic diagram of an I/O circuit combining a pluralityof sequential logic circuits.

FIG. 2C is a schematic diagram of an 8-bit I/O circuit.

FIG. 3 is an operational flowchart of an I/O circuit.

FIG. 4A is a first schematic diagram of a serial to parallel I/O circuitaccording to the present invention.

FIG. 4B is a second schematic diagram of a serial to parallel I/Ocircuit according to the present invention.

FIG. 5 is an operational flowchart of a method for serial to parallel ofan I/O circuit according to the present invention.

FIG. 6 is an operational flowchart of a method for serial to parallel ofan 8-bit I/O circuit according to the present invention.

Table 1 is a status diagram of the output and input of a 8-bit I/Ocircuit.

Table 2 is a truth table of a multiplexer.

Table 3 is a status diagram of the output and input of a 8-bit I/Ocircuit of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides an apparatus and method for serial toparallel of an I/O circuit that enables the I/O circuit to output theinput data stream quickly without latency. The description will be givenwith an embodiment hereinafter. However, those skilled in the art willunderstand that it is only an example, and is not used to limit theinvention itself. The embodiment related to the present invention willbe described in detail below.

FIG. 4A shows a serial to parallel apparatus 400 of an I/O circuitaccording to one embodiment of the present invention, and FIG. 4B showsa detailed structural diagram of FIG. 4A. The circuit shown in FIG. 4Bcomprises M sequential logic circuits SL (SL₀, SL₁, . . . , SL_(M−1)),while each sequential logic circuit includes a first D-type flip-flop, asecond D-type flip-flop, a multiplexer, and a D-type latch. One of firstD-type flip-flops D₁ (D₁₀, D₁₁, . . . , D_(1M−1)) receives one bit ofinput data, and the output of each first D-type flip-flop is directed tothe input of a first D-type flip-flop of a next stage. For example, theoutput of the flip-flop D₁₀ is coupled with the input of a flip-flopD₁₁, which is the next stage of the flip-flop D₁₀. One of second D-typeflip-flops D₂ (D₂₀, D₂₁, . . . , D_(2M−1)) receives one bit of an enablecontrol signal, and the output of each second D-type flip-flop isdirected to the input of a second D-type flip-flop of a next stage. Forexample, the output of the flip-flop D₂₀ is coupled to the input of aflip-flop D₂₁, which is the next stage of the flip-flop D₂₀. Each one ofmultiplexers MUX (MUX₀, MUX₁, . . . , or MUX_(M−1)) has two inputterminals, while one of which is connected to the output of acorresponding D-type flip-flop so as to receive the input data receivedby relative first D-type flip-flops. For example, the flip-flop D₁₀ willdirect the input data it received to the first multiplexer MUX₀.Additionally, each multiplexer further has an enable control signalreceiving terminal connected to the output of a corresponding secondD-type flip-flop, used for receiving an enable control signal receivedby the second D-type flip-flop. For example, the first multiplexer MUX₀connected to a first second D-type flip-flop D₂₀ will receive an enablecontrol signal delivered from the flip-flop D₂₀. One of D-type latchesD_(G) (D_(G0), D_(G1), . . . , D_(GM−1)) connects to a correspondingmultiplexer so as to output the data selected by the correspondingmultiplexer, and the output data is fed back to another input terminalof the corresponding multiplexer, which is also taken as feedback dataso as to be selected for data output when a next set of input data areinput. For example, a first D-type latch D_(G0) connected to a firstmultiplexer MUX₀ outputs the data selected by the first multiplexerMUX₀, and feeds back its output data to another input terminal of thefirst multiplexer MUX₀. As shown in FIG. 4B, M first D-type flip-flopsD₁ (D₁₀, D₁₁, . . . , D_(1M−1)) are combined to form a first shiftregister 410, while M second D-type flip-flops D₂ (D₂₀, D₂₁, . . . ,D_(2M−1)) are combined to form a second shift register 420.

A method for serial to parallel of an I/O circuit of the presentinvention is as follows. First a clear signal CLR is asserted to allfirst D-type flip-flops D₁ (D₁₀, D₁₁, . . . , D_(1M−1)) and all secondD-type flip-flops D₂ (D₂₀, D₂₁, . . . , D_(2M−1)), respectively, so asto clear out previously input signals stored therein. At which time thedata in all the first D-type flip-flop D₁ (D₁₀, D₁₁, . . . , D_(1M−1))are each null, the enable control signals in all the second D-typeflip-flops D₂ (D₂₀, D₂₁, . . . , D_(2M−1)) are each of a low level (0),therefore the system will select to keep the original output status. Atruth table related to operation of one of the multiplexers is as shownin Table 2. When the enable control signal is of a high level (1), amultiplexer selects the input data as its output, and when the enablecontrol signal is of a low level (0), the multiplexer selects thefeedback data as its output. Next, an N-bit input data stream I (I₀ . .. I_(N−3)I_(N−2)I_(N−1)) and an N-bit enable control signal stream E (E₀. . . E_(N−3)E_(N−2)E_(N−1)) are input simultaneously. The input datastream I and the enable control signal E are input into the flip-flopD₁₁ and the flip-flop D₂₀, respectively, one bit each time according tothe bit sequence, and the two signals are controlled by a clock signalCLK simultaneously.

When triggered by the clock signal CLK, the flip-flop D₁₀ receives afirst set of input data I₀, while the flip-flop D₂₀ receives a first setof enable control signals E₀. When triggered again by the clock signalCLK, the second set of input data I₁ and the second set of enablecontrol signals E₁ are input into the flip-flop D₁₀ and the flip-flopD₂₀, respectively. I₀ is simultaneously output to the input terminal ofthe first multiplexer MUX₀ and the flip-flop D₁₁, and E₀ issimultaneously output to the enable control signal receiving terminal ofthe first multiplexer MUX₀ and flip-flop D₂₁. At this time, the firstmultiplexer MUX₀ selects to output I₀ according to the status of thereceived enable control signal E₀ (suppose that E₀ is of a high level(1)), then delivers I₀ to the first D-type latch D_(G0) for latching.The first D-type latch D_(G0) does not output I₀ until triggered by theclock signal Load, and meanwhile I₀ is fed back to another inputterminal of the first multiplexer MUX₀ as feedback data, so as to beselected as the output for the next set of data.

Next, when triggered again by the clock signal CLK, a third set of inputdata I₂ and a third set of enable control signals E₂ are input into theflip-flop D₁₀ and the flip-flop D₂₀ respectively. I₁ is simultaneouslyoutput to an input terminal of the first multiplexer MUX₀ and theflip-flop D₁₁, while E₁ is simultaneously output to the enable controlsignal receiving terminal of the first multiplexer MUX₀ and theflip-flop D₂₁. On the other hand, I₀ is simultaneously output to theinput terminal of the second multiplexer MUX₁ and the third first D-typeflip-flop D₁₂, and E₀ is simultaneously output to the enable controlsignal receiving terminal of the second multiplexer MUX₁ and a thirdsecond D-type flip-flop D₂₂. At this time, the first multiplexer MUX₀selects to output the input data I₁ or the feedback data I₀ according tothe status of the received enable control signal E₁ (i.e., I₁ isselected to be output when the enable control signal E₁ received by thefirst multiplexer MUX₀ is of a high level (1), and I₀ is selected to beoutput when the enable control signal E₁ received by the firstmultiplexer MUX₀ is of a low level (0)). Likewise, the secondmultiplexer MUX₁ will also select data to output (I₀ or the output datapreviously fed back) based on the status of the received enable controlsignal E₀. Finally the data selected by the first multiplexer MUX₀ andthe second multiplexer MUX₁ are sent to the first D-type latch D_(G0)and the second D-type latch D_(G1) for latching, and will be outputsimultaneously after triggered again by the clock signal Load. Theoutput data thereof are fed back to another input terminal of each ofthe first multiplexer MUX₀ and the second multiplexer MUX₁ as to befeedback data so as to be selected as output for a next set of dataoutput. The input status of subsequent data may be performed similarly,but it should be noted that both M and N are positive integers greaterthan 1.

FIG. 5 shows an operational flowchart according to an embodiment of thepresent invention, the steps thereof are as follows:

Step 510: assert a clear signal CLR;

Step 520: input an input data stream I (I₀ . . . I_(N−3)I_(N−2)I_(N−1))and an enable control signal stream E (E₀ . . . E_(N−3)E_(N−2)E_(N−1));

Step 530: triggered by a clock signal CLK, input the input data stream Iand the enable control signal stream E sequentially into the flip-flopD₁₀ and the flip-flop D₂₀, respectively, one bit each time according tobit sequence;

Step 540: triggered again by the clock signal CLK, send previouslyobtained input data I_(a) (0≦a≦N−1, a should be an integer) into a firstD-type flip-flop of a next stage and the input terminal of acorresponding multiplexer, and send the enable control signal E_(a)(0≦a≦N−1, a should be an integer) to a second D-type flip-flop of thenext stage and the enable control signal receiving terminal of thecorresponding multiplexer MUX;

Step 550: after the corresponding multiplexer MUX receives the inputdata I_(a) (0≦a≦N−1, a should be an integer) and the enable controlsignal E_(a) (0≦a≦N−1, a should be an integer), the correspondingmultiplexer MUX selects to output the input data I_(a) (0≦a≦N−1) orfeedback data I_(a−1) (0≦a≦N−1) previously fed back according to thestatus of the enable control signal E_(a) (0≦a≦N−1, a should be aninteger);

Step 560: direct the data (I_(a) or I_(a−1)) selected by thecorresponding multiplexer to a corresponding D-type latch D_(G) forlatching; and

Step 570: triggered by a clock signal Load to output the selected dataand feed back them to the corresponding multiplexers.

Taking the serial to parallel of an 8-bit I/O circuit as an example, the8-bit serial to parallel I/O circuit comprises 8 sequential logiccircuits SL (SL₀, SL₁, SL₂, SL₃, SL₄, SL₅, SL₆, SL₇) in seriesconnection. The eight sequential logic circuits SL (SL₀, SL₁, SL₂, SL₃,SL₄, SL₅, SL₆, SL₇) include 8 first D-type flip-flops D₁ (D₁₀, D₁₁, D₁₂,D₁₃, D₁₄, D₁₅, D₁₆, D₁₇), eight second D-type flip-flops D₂ (D₂₀, D₂₁,D₂₂, D₂₃, D₂₄, D₂₅, D₂₆, D₂₇), eight multiplexers MUX (MUX₀, MUX₁, MUX₂,MUX₃, MUX₄, MUX₅, MUX₆, MUX₇), and eight D-type latches D_(G) (D_(G0),D_(G1), D_(G2), D_(G3), D_(G4), D_(G5), D_(G6), D_(G7)). In addition,the 8-bit serial to parallel I/O circuit further comprises an N-bitinput data stream I (I₀ . . . I_(N−3)I_(N−2)I_(N−1)), an N-bit enablecontrol signal stream E (E₀ . . . E_(N−3)E_(N−2)E_(N−1)), a clear signalCLR, a clock signal CLK and a clock signal Load.

The flowchart thereof is as shown in FIG. 6:

Step 602: input a clear signal CLR;

Step 604: wait for the input of an N-bit input data stream I (I₀ . . .I_(N−3)I_(N−2)I_(N−1)) and an N-bit enable control signal stream E (E₀ .. . E_(N−3)E_(N−2)E_(N−1));

Step 606: set an initial value a=0 (0≦a≦N−1);

Step 608: triggered by a clock signal CLK so as to synchronously inputthe input signal Ia and the enable control signal Ea into D₁₀ and D₂₀,respectively;

Step 610: determine whether a is 0, and if a is 0, jump to step 612,otherwise jump to step 616;

Step 612: let a=a+1

Step 614: determine whether a is greater than N−1, and if yes, finishthe input, if no, return to step 608;

Step 616: set an initial value b=a−1 and k=0;

Step 618: input I_(b) into MUX_(k) and D_(1k+1), and input E_(b) intoMUX_(k) and D_(2k+1);

Step 620: determine whether b is 0, and if b is not 0, jump to step 622,otherwise jump to step 624;

Step 622: let b=b−1 and k=k+1, then jump to step 618 and step 620;

Step 624: multiplexers select one of the input data and the fed backdata according to the enable control signals obtained respectively;

Step 626: triggered by a clock signal Load to send the selected data toa corresponding D-type latch for storing; and

Step 628: triggered again by the clock signal Load to output the dataand feedback it to the corresponding multiplexer.

As can be seen from Table 3, an 8-bit I/O circuit output and inputstatus table, if only one bit of data is modified, in comparison withthe prior art that the output will not be made until 8 bits of data arewritten, the I/O efficiency of the present invention is enhanced by 8times (only ⅛ of the original time is needed). Additionally, if two bitsof data are to be modified, then in comparison with the prior art, theI/O efficiency of the present invention is enhanced by 4 times (only ¼of the original time is needed).

The apparatus and method for serial to parallel of an I/O circuitaccording to the present invention does not necessary to wait for thesequential logic circuits being fully written data before outputaltogether. That is, each time when one bit of data is input, the systemcan make an output at once, thus what is needed is to complete the inputof all the necessary number of data bits. Therefore, in comparison withthe prior art that the output can only be made until the sequentiallogic circuits are fully written, the present invention features highspeed, saves time and enhances the I/O efficiency.

While the present invention is described above with respect to apreferred embodiment of an 8-bit I/O circuit, it is not used to definethat the spirit and inventive entity of the present invention is limitedto the above embodiments. It can contain arbitrary bits I/O circuit,which is covered by the spirit of the present invention. Therefore, allmodifications without departing from the spirit and scope of the presentinvention are contained in the scope of the attached claims.

1. A sequential logic circuit comprising: a selecting element including:a first input terminal for receiving a first input signal; a secondinput terminal for receiving a second input signal; an enable controlsignal receiving terminal for receiving an enable control signal so asto determine whether the selecting element selects the first inputsignal or the second input signal; and an input terminal; a firststorage element, an output terminal of the first storage element beingcoupled to the first input terminal of the selecting element, forsending an input data received by an input terminal of the first storageelement to the selecting element as a first input signal; a secondstorage element, an output terminal of the second storage element beingcoupled to the enable control signal receiving terminal of the selectingelement, for sending the enable control signal received by an inputterminal of the first storage element to the selecting element; and athird storage element, the input terminal of the third storage elementbeing coupled to an output terminal of the selecting element, foroutputting a data selected by the selecting element, and feeding backthe data output by the selecting element to the second input terminal ofthe selecting element so as to be selected as a second input signal foroutputting a next set of data signals.
 2. The sequential logic circuitaccording to claim 1, wherein the selecting element selects the firstinput signal for selecting the data selected by the first storageelement as an output of the third storage element when the enablecontrol signal is of a first level.
 3. A serial to parallel input/outputcircuit, comprising a plurality of selecting elements, each including: afirst input terminal for receiving a first input signal; a second inputterminal for receiving a second input signal; an enable control signalreceiving terminal for receiving an enable control signal so as todetermine whether the selecting element selects the first input signalor the second input signal; and an input terminal; a plurality of firststorage elements, each of the first storage elements for receiving aninput data, wherein an output terminal of each of the first storageelements is coupled to an input terminal of a next first storage elementand also coupled to the first input terminal of a corresponding one ofthe plurality of selecting elements, for sending an input data receivedby a first input terminal to the corresponding selecting element as afirst input signal; a plurality of second storage elements, each of thesecond storage elements for receiving an enable control signal, whereinan output terminal of each of the second storage elements is coupled toan input terminal of a next second storage element and also coupled toan enable control signal receiving terminal of a corresponding one ofthe plurality of selecting elements, for sending an enable controlsignal received by the second storage element to the correspondingselecting element; and a plurality of third storage elements, wherein aninput terminal of each of the third storage elements is coupled to anoutput terminal of a corresponding selecting element, for outputting adata selected by the corresponding selecting element and feeding backthe data signal output by the selecting element to a second inputterminal of the selecting element so as to be selected as a second inputsignal for outputting a next set of data signals, wherein bits of aninput data signal stream are input into the first storage elementssequentially and can be output at once as soon as having received theinput data signal, without waiting for all the data are written in theplurality of first storage elements.
 4. The serial to parallelinput/output circuit according to claim 3, wherein when a next inputdata is input, the first storage element sends the input data alreadyreceived to a first storage element of a next stage.
 5. The serial toparallel input/output circuit according to claim 3, wherein the enablecontrol signal stream is input into the second storage element one biteach time as the enable control signal according to bit sequence, andwhen a next enable control signal is input, the second storage elementsends the enable control signal already received to a second storageelement of a next stage.
 6. The serial to parallel input/output circuitaccording to claim 3, wherein: when the enable control signal receivedby the second storage element is of a first level, the correspondingselecting element selects the first input signal for selecting the inputdata received by the corresponding first storage element as the outputof the third storage element; and when the enable control signalreceived by the second storage element is of a second level, thecorresponding selecting element selects the second input signal forselecting the feedback data fed back by the previous outputting as theoutput of the third storage element so as to keep the output of thethird storage element unchanged.
 7. A method for serial to parallel ofan input/output circuit system outputs an input data at once withoutwaiting for the serial to parallel input/output circuit system to finisha writing of all the input data, comprising the steps of: inputting aninput data, wherein the input data is one bit of an input data stream,and the input data stream is input into a serial to parallelinput/output circuit system sequentially and each time one bit of theinput data is input; inputting an enable control signal, wherein: whenthe enable control signal is of a first level, the serial to parallelinput/output circuit system selecting the input data as its output; andwhen the enable control signal is of a second level, the serial toparallel input/output circuit system selecting a feedback data as itsoutput; and outputting a data from the input data or the feedback dataaccording to the enable control signal.
 8. The method for serial toparallel of an input/output circuit according to claim 7, wherein aprevious set of output data is fed back to the serial to parallelinput/output circuit system to formed as the feedback data.
 9. Themethod for serial to parallel of an input/output circuit according toclaim 7, wherein the enable control signal is one bit of an enablecontrol signal stream, and the enable control signal stream is inputinto the serial to parallel input/output circuit system sequentially.10. The method for serial to parallel of an input/output circuitaccording to claim 7, wherein the enable control signal and the inputdata are synchronous.